1. Technical Field
The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern of a semiconductor device using double spacer patterning technology.
2. Related Art
With reduction in a design rule of a semiconductor device, it is difficult to form a line/space pattern of 38 nm or less through a conventional exposure method using ArF immersion exposure equipment that employs a numerical aperture (NA) of 1.35 or less. An exposure source (extreme ultraviolet (EUV) having a wavelength of 13.4 nm) has been used to develop a pattern of 30 nm or less. However, it is difficult to apply the EUV process at a production level due to various limitations in exposure source power, mechanism, reticle, lack of resist, and the like.
Therefore, spacer patterning technology (STP) has been applied to form an isolation layer, a control gate (CGT), and a metal layer (MT1 layer) of 20 to 30 nm-graded NAND flash memories, in which line/space patterns of a cell area are mainly formed, and to form an isolation layer (6F2 structure) of 30 nm-graded DRAMs. Application of double patterning technology (DPT) to a process of forming a complicated bit line (BL) core in DRAMs in which various patterns are mixed has also been considered.
Further, as a gate electrode such as a conventional recess gate or a conventional fin-gate, which includes a stacked structure of silicon oxynitride, polysilicon, tungsten (SiON/poly-Si/W), is formed on an active region and as a gate electrode material is in direct contact with a gate dielectric layer, polysilicon having a work function of about 4.1 eV is employed. Meanwhile, for a buried gate structure, a direct metal gate type of a stacked structure including silicon oxynitride, titanium nitride, tungsten (SiON/TiN/W) is employed. For the titanium nitride, a material having a work function of about 4.5 eV is used.
In the buried gate structure, since the gate electrode is buried below a silicon surface, a probability of self-aligned contact (SAC) fail related to a word line (gate) is low and a word line is formed separate from a bit line and thus parasitic capacitance can be reduced. Therefore, a unit cell size can be reduced and thus a net die is increased.
There is a need for methods for reducing a width of the buried gate to increase an integration level of the device having the buried gate structure.